1. Field of the Invention
The present invention relates generally to systems and methods for performing quantization such as might be required for data compression. More particularly, the present invention relates to an efficient method of using single-instruction, multiple-data (SIMD) instructions to perform quantization.
2. Description of the Related Art
As multimedia applications become more sophisticated, they demand increasing amounts of storage and transmission bandwidth. To combat this tendency, multimedia systems use various types of audio/visual compression algorithms to reduce the amount of necessary storage and transfer bandwidth. In general, different video compression methods exist for still graphic images and for full-motion video. Intraframe compression methods are used to compress data within a still image or single frame using spatial redundancies within the frame. Interframe compression methods are used to compress multiple frames, i.e., motion video, using the temporal redundancy between the frames. Interframe compression methods are used exclusively for motion video, either alone or in conjunction with intraframe compression methods.
Intraframe or still image compression techniques generally use frequency domain techniques, such as the two-dimensional discrete cosine transform (2D-DCT). The frequency domain characteristics of a picture frame generally allow for easy removal of spatial redundancy and efficient encoding of the frame. One video data compression standard for still graphic images is JPEG (Joint Photographic Experts Group) compression. JPEG compression is actually a group of related standards that use the discrete cosine transform (DCT) to provide either lossless (no image quality degradation) or lossy (imperceptible to severe degradation) compression. Although JPEG compression was originally designed for the compression of still images rather than video, JPEG compression is used in some motion video applications.
In contrast to compression algorithms for still images, most video compression algorithms are designed to compress full motion video. As mentioned above, video compression algorithms for motion video use a concept referred to as interframe compression to remove temporal redundancies between frames. Interframe compression involves storing only the differences between successive frames in the data file. Interframe compression stores the entire image of a key frame or reference frame, generally in a moderately compressed format. Successive frames are compared with the key frame, and only the differences between the key frame and the successive frames are stored. Periodically, such as when new scenes are displayed, new key frames are stored, and subsequent comparisons begin from this new reference point. The difference frames are further compressed by such techniques as the 2D-DCT. Examples of video compression which use an interframe compression technique are MPEG (Moving Pictures Experts Group), DVI and Indeo, among others.
MPEG compression is based on two types of redundancies in video sequences, these being spatial, which is the redundancy in an individual frame, and temporal, which is the redundancy between consecutive frames. Spatial compression is achieved by considering the frequency characteristics of a picture frame. Each frame is divided into non-overlapping blocks, and each block is transformed via the 2D-DCT. After the transformed blocks are converted to the xe2x80x9cDCT domainxe2x80x9d, each entry in the transformed block is quantized with respect to a set of quantization tables. The quantization step for each entry can vary, taking into account the sensitivity of the human visual system (HVS) to the frequency. Since the HVS is more sensitive to low frequencies, most of the high frequency entries are quantized to zero. In this step where the entries are quantized, information is lost and errors are introduced to the reconstructed image. Run length encoding is used to transmit the quantized values. To further enhance compression, the blocks are scanned in a zig-zag ordering that scans the lower frequency entries first, and the non-zero quantized values, along with the zero run lengths, are entropy encoded.
As discussed above, temporal compression makes use of the fact that most of the objects remain the same between consecutive picture frames, and the difference between objects or blocks in successive frames is their position in the frame as a result of motion (either due to object motion, camera motion or both). This relative encoding is achieved by the process of motion estimation. The difference image as a result of motion compensation is further compressed by means of the 2D-DCT, quantization and RLE entropy coding.
When an MPEG decoder receives an encoded stream, the MPEG decoder reverses the above operations. Thus the MPEG decoder performs inverse scanning to remove the zig zag ordering, inverse quantization to de-quantize the data, and the inverse 2D-DCT to convert the data from the frequency domain back to the pixel domain. The MPEG decoder also performs motion compensation using the transmitted motion vectors to recreate the temporally compressed frames.
Quantization is an important part of many compression techniques, including the JPEG and MPEG compression standards. For color images, the quantization step must be performed between two and three times per pixel, depending on the compression technique. As a result, the quantization step may easily need to be performed more than 15 million times per second when compressing video images in real time.
Traditional x86 processors are not well adapted for the types of calculations used in signal processing. Thus, signal processing software applications on traditional x86 processors have lagged behind what was realizable on other processor architectures. There have been various attempts to improve the signal processing performance of x86-based systems. For example, microcontrollers optimized for digital signal processing computations (DSPs) have been provided on plug-in cards or the motherboard. These microcontrollers operated essentially as hardwired coprocessors enabling the system to perform signal processing functions.
As multimedia applications become more sophisticated, the demands placed on computers are redoubled. Microprocessors are now routinely provided with enhanced support for these applications. For example, many processors now support single-instruction multiple-data (SIMD) commands such as MMX instructions. Advanced Micro Devices, Inc. (hereinafter referred to as AMD) has proposed and implemented 3DNow!(trademark), a set of floating point SIMD instructions on x86 processors starting with the AMD-K6(copyright)-2. The AMD-K6(copyright)-2 is highly optimized to execute the 3DNow!(trademark)instructions with minimum latency. Software applications written for execution on the AMD-K6(copyright)-2 may use these instructions to accomplish signal processing functions and the traditional x86 instructions to accomplish other desired functions.
The 3DNow! instructions, being SIMD commands, are xe2x80x9cvectoredxe2x80x9d instructions in which a single operation is performed on multiple data operands. Such instructions are very efficient for graphics and audio applications where simple operations are repeated on each sample in a stream of data. SIMD commands invoke parallel execution in superscalar microprocessors where pipelining and/or multiple execution units are provided.
Vectored instructions typically have operands that are partitioned into separate sections, each of which is independently operated upon. For example, a vectored multiply instruction may operate upon a pair of 32-bit operands, each of which is partitioned into two 16-bit sections or four 8-bit sections. Upon execution of a vectored multiply instruction, corresponding sections of each operand are independently multiplied. So, for example, the result of a vectored multiplication of [3;5] and [7;11] would be [21;55]. To quickly execute vectored multiply instructions, microprocessors such as the AMD-K6xc2x0-2 use a number of multipliers in parallel.
FIG. 1 illustrates one embodiment of a representative computer system 100 such as the AMD-K6(copyright)-2 which is configured to support the execution of general-purpose instructions and parallel floating-point instructions. Computer system 100 may comprise a microprocessor 110, memory 112, bus bridge 114, peripheral bus 116, and a plurality of peripheral devices P1-PN. Bus bridge 114 couples to microprocessor 110, memory 112 and peripheral bus 116. Bus bridge 114 mediates the exchange of data between microprocessor 110, memory 112 and peripheral devices P1-PN.
Microprocessor 110 is a superscalar microprocessor configured to execute instructions in a variable length instruction set. A subset of the variable length instruction set is the set of SIMD (simultaneous-instruction multiple-data) floating-point instructions. Microprocessor 110 is optimized to execute the SIMD floating-point instructions in a single clock cycle. In addition, the variable length instruction set includes a set of x86 instructions (e.g. the instructions defined by the 80486 processor architecture).
Memory 112 stores program instructions which control the operation of microprocessor 110. Memory 112 additionally stores input data to be operated on by microprocessor 110, and output data generated by microprocessor 110, in response to the program instructions. Peripheral devices P1-PN are representative of devices such as network interface cards (e.g. Ethernet cards), modems, sound cards, video acquisition boards, data acquisition cards, external storage media, etc. Computer system 100 may be a personal computer, a laptop computer, a portable computer, a television, a radio receiver and/or transmitter, etc.
FIG. 2 illustrates one embodiment for microprocessor 110. Microprocessor 110 may be configured with 3DNow!(trademark)and MMX(copyright) technologies. Microprocessor 110 may comprise bus interface unit 202, predecode unit 204, instruction cache 206, decode unit 208, execution engine 210, and data cache 214. Microprocessor 110 may also include store queue 212 and an L2 cache 216. Additionally, microprocessor 110 may include a branch prediction unit and a branch resolution unit (not shown) to allow efficient speculative execution.
Predecode unit 204 may be coupled to instruction cache 206, which stores instructions received from memory 112 via bus interface unit 202 and predecode unit 204. Instruction cache 206 may also contain a predecode cache (not shown) for storing predecode information. Decode unit 208 may receive instructions and predecode information from instruction cache 206 and decode the instructions into component pieces. The component pieces may be forwarded to execution engine 210. The component pieces may be RISC operands. (Microprocessor 110 may be RISC-based superscalar microprocessor). RISC ops are fixed-format internal instructions, most of which are executable by microprocessor 110 in a single clock cycle. RISC operations may be combined to form every function of the x86 instruction set. Execution engine 210 may execute the decoded instructions in response to the component pieces received from decode unit 208. As shown in FIG. 3, execution engine 210 may include a scheduler buffer 302 coupled to receive input from decode unit 208. Scheduler buffer 302 may be configured to convey decoded instructions to a plurality of execution pipelines 306-314 in accordance with input received from instruction control unit 304. Execution pipelines 306-314 are representative, and in other embodiments, varying numbers and kinds of pipelines may be included.
Instruction control unit 304 contains the logic necessary to manage out of order execution of instructions stored in scheduler buffer 302. Instruction control unit 304 also manages data forwarding, register renaming, simultaneous issue and retirement of RISC operations, and speculative execution. In one embodiment, scheduler buffer 302 holds up to 24 RISC operations at one time. When possible, instruction control unit 304 may simultaneously issue (from buffer 302) a RISC operation to each available execution unit.
Execution pipelines 306-315 may include load unit 306, store unit 308, X pipeline 310, Y pipeline 312, and floating point unit 314. Load unit 306 may receive input from data cache 214, while store unit 308 may interface to data cache 214 via a store queue 212. Store unit 308 and load unit 306 may be two-staged pipeline designs. Store unit 308 may perform memory writes. For a memory write operation, the store unit 308 may generate a physical address and the associated data bytes which are to be written to memory. These results (i.e. physical address and data bytes) may be entered into the store queue 212. Memory read data may be supplied by data cache 214 or by an entry in store queue 212 (in the case of a recent store).
X pipeline 310 and Y pipeline 312 may each include a combination of integer, integer SIMD (e.g. MMX(copyright)), and floating-point SIMD (e.g. 3DNOW!(trademark)) execution resources. Some of these resources may be shared between the two register pipelines. As suggested by FIG. 3, load unit 306, store unit 308, and pipelines 310, 312 may be coupled to a set of registers 316 from which these units are configured to read source operands. In addition, load unit 306 and pipelines 310, 312 may be configured to store destination result values to registers 316. Registers 316 may include physical storage for a set of architected registers.
Floating point unit 314 may also include a set of floating point registers (not shown separately). Floating point unit 314 may execute floating point instructions (e.g. x87 floating point instructions, or IEEE 754/854 compliant floating point instructions) designed to accelerate the performance of scientific software. Floating point unit 314 may include an adder unit, a multiplier unit, and a divide/square-root unit, etc. Floating point unit 314 may operate in a coprocessor-like fashion, in which decode unit 208 directly dispatches the floating point instructions to unit 314. The floating point instructions may still be allocated in scheduler buffer 302 to allow for in-order retirement of instructions. Unit 314 and scheduler buffer 302 may communicate to determine when a floating point instruction is ready for retirement.
Pipelines 310, 312 include resources that allow them to perform scalar integer operations, SIMD integer operations, and SIMD floating point operations. The SIMD integer operations that are performed correspond to the MMX(copyright) instruction set architecture, and the SIMD floating point operations that are performed correspond to the 3DNow!(trademark) instruction set. Any pair of operations which do not require a common resource may be simultaneously executed in the two pipelines (i.e. one operation per pipeline). Thus, the maximum rate of execution for the two pipelines taken together is equal to two operations per cycle.
Registers 316 may include registers which are configured to support packed integer and packed floating-point operations (e.g. registers denoted MM0 through MMn which conform to the 3DNow!(trademark) and MMX(copyright) instruction set architectures). In one embodiment of microprocessor 110, there are eight MM registers, i.e. MM0 through MM7, each having a 64 bit storage capacity. Two 32-bit floating point operands may be loaded into each MM register in a packed format. For example, suppose register MM0 has been loaded with floating-point operands A and B, and register MM1 has been loaded with floating-point operands C and D. In shorthand notation, this situation may be represented by the expressions MM0=[A:B] and MM1=[C:D], where the first argument in a bracketed pair represents the high-order 32 bits of a quadword register, and the second argument represents the low-order 32 bits of the quadword register. The 3DNow!(trademark) instructions invoke parallel floating-point operations on the contents of the MM registers. For example, the 3DNow!(trademark) multiply instruction given by the assembly language construct xe2x80x9cpfmul MM0,MM1xe2x80x9d invokes a parallel floating-point multiply on corresponding components of MM0 and MM1. The two floating-point resultant values of the parallel multiply are stored in register MM0. Thus, after the instruction has completed execution, register MM0 may be represented by the expression MM0=[A*C:B*D]. As used herein, the assembly language construct
xe2x80x9cpfxxx MMdest, MMsrcxe2x80x9d
implies that a 3DNow!(trademark) operation corresponding to the mnemonic pfxxx uses registers MMdest and MMsrc as source operands, and register MMdest as a destination operand.
The assembly language construct
xe2x80x9cpfadd MM0,MM1xe2x80x9d
invokes a parallel floating-point addition on corresponding components of registers MM0 and MM1. Thus, after this instructions has completed execution, register MM0 may be represented by the expression MM0=[A+C:B+D]. Various MMX and 3DNow! instructions are described in greater detail in AMD""s xe2x80x9c3DNow! Technology Manualxe2x80x9d and AMD""s xe2x80x9cAMD Extensions to the 3DNow! and MMX Instruction Sets Manualxe2x80x9d, both of which are incorporated herein by reference.
It is noted that alternate embodiments of microprocessor 110 are contemplated where the storage capacity of an MM register allows for more than two floating-point operands. For example, an embodiment of microprocessor 110 is contemplated where the MM registers are configured to store four 32-bit floating-point operands. In this case, the MM registers may have a size of 128-bits.
Video compression operations in multimedia systems generally require a large amount of processing. For example, hundreds of multiplication (or division) operations as well as hundreds of addition (or subtraction) operations may be required to perform the 2D-DCT or IDCT upon a single 8xc3x978 array. Such computational requirements can be extremely time-consuming and resource intensive when hundred of thousands of 8xc3x978 blocks are processed every second.
A new system and method are desired for efficiently performing compression in multimedia systems. It is particularly desirable to perform repeated, low-level operations such as quantization as efficiently as possible to minimize computational requirements and make such compression feasible in a general purpose computer system.
The problems outlined above are in large part solved by a method of quantizing multiple input values in parallel using SIMD instructions. In one embodiment, the method comprises (1) receiving a set of input values Xi; (2) operating on the set of input values to produce a set of binary mask values Ki that are related to the input values Xi by Ki=xe2x88x921 if Xi greater than 0, and Ki=0 if Xixe2x89xa60; (3) adding half of a quantization step Q to the input values Xi to obtain sum values; (4) subtracting half of a quantization step Q to the input values Xi to obtain difference values; (5) using the binary mask values to screen out sum values calculated from negative input values; (6) using a complementary binary mask to screen out difference values calculated from positive input values; and (7) combining the screened sum and difference values to determine prequantization values Yi that can be expressed Yi=Xi+Q/2 if Xi greater than 0, and Yi=Xixe2x88x92Q/2 if Xixe2x89xa60. The prequantization values may then be converted to floating point format, divided by Q, and restored to integer format to obtain the desired quantization values. Each of these operations can be performed in parallel on each of the values in the set using SIMD instructions such as packed word add with saturation (PADDSW), packed word subtract with saturation (PSUBSW), packed compare word for greater than (PCMPGTW), packed floating point to packed double-word integer (PF2ID), and packed word integer to packed floating point (PI2FW).